Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs

Boutchacha, T. and Ghibaudo, G. and Gift, Stephan (2020) Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs. Active and Passive Electronic Components, 2020. pp. 1-10. ISSN 0882-7516

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Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

1. Introduction
Fully Depleted (FD) Silicon-On-insulator (SOI) is considered as one of the candidates for the future sub 14 nm CMOS generations. The use of ultrathin body and thin buried oxide (UTBB) enables to enhance the technology scalability, providing a very good control of the short-channel effect (SCE), as well as back-to-front gate coupling effects useful for threshold voltage Vth control with efficient body bias effect [1, 2].

The study of low-frequency noise (LF) in the UTBB FDSOI is of great interest because it is a key issue for the technology evaluation for identifying the traps possibly introduced during the device processing. Moreover, it is not only limiting the analog circuit operation, but it should also jeopardize the digital circuit functioning for aggressively scaled devices.

The analysis of LF noise in FD-SOI devices is a more complicated task compared to their bulk ancestors. In SOI instead of one interface, as in bulk devices, there are two interfaces, the so-called front and back ones, that can influence the noise behaviour due to the strong electrostatic coupling between them.

It is now well accepted that the LF 1/f noise in FDSOI and multigate devices mostly stems from the fluctuations of the inversion charge nearby the two interfaces [3–11]. For UTBB devices, the gate oxide thickness reaches dimensions as small as nanometers, leading to larger surface roughness scattering playing an important role on carrier mobility and drain current fluctuations [12].

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Depositing User: APLOS Library
Date Deposited: 11 Jun 2022 07:23
Last Modified: 11 Jun 2022 07:23

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